1. Field of the Invention
The present invention generally relates to a method for forming an embedded non-volatile memory, and more particularly to a method for forming an embedded non-volatile memory with double poly layer and double spacer.
2. Description of the Prior Art
Typical semiconductor memory utilized during microprocessor operation is volatile. That is in the case of power interruption, the data stored in the semiconductor memory is typically completely lost. One way to circumvent this problem is to provide separate backup of the memory, such as battery power or capacitor storage. An alternate technique is to make the memory fundamentally non-volatile. This option is highly desirable because non-volatile semiconductor memories would not only withstand, power interruption, but also would be stored or shipped without being energized.
Non-volatile memory devices are important for providing an advantage that random access memory (RAM), both dynamic and static, can""t be provided. That is, non-volatile memory devices do not lose their memory even the power is turned off. RAM enables information to be both stored and read to a memory cell as dictated by a microprocessor. Read-only memory (ROM) is the most popular variety of non-volatile memory devices.
However, the flash memory is electrically re-programmable for a limited number of times. This makes it ideal for those applications where only a few changes in the programming of the system is for either the entire memory array or for blocks of it.
Besides, memory storage exists not only as stand-alone memory device, but also embedded in processor chips. The performance of an embedded flash can be better than other flash since bandwidth problems are reduced and interface circuit and package leads are eliminated. It can also have characteristic tailored to the specific application rather than being a standardized comprises between many factors such as high operating speed.
Referring to FIG. 1A, the substrate 100 is divided into at least a memory array area 100a and a logic device area 100b. An ONO layer (oxide/nitride/oxide layer) 102 is on the substrate 100. The conventional method for forming the first dielectric layer (tunneling oxide layer) 102a on the substrate 100 by thermal oxidation. However, the dielectric constant value of first 102a and second dielectric layer 102c is about 3.8 to 3.9 and thermal oxidation is a high temperature process. Then, a charge storage layer 102b such as silicon nitride (SiN) is formed on the first dielectric layer 102a by conventional CVD method (chemical vapor deposition method). Next, a second dielectric layer 102c is formed on the charge storage layer 102b by conventional CVD method. The material of first 102a and second dielectric layer 102c is silicon oxide. According to the hot electron injection phenomenon (HEI), some hot electrons penetrate through the bottom first dielectric layer 102a, especially when first dielectric layer 102a is thin enough, and electrons are therefore collected in charge storage layer 102b. Then, a photoresist layer is formed on the ONO layer 102 and a bit line structure is formed in the substrate 100 by using bit line ion implantation.
Then, referring to FIG. 1B, a photoresist layer 104 is formed on the second dielectric layer 102c. Then, an etching process is to remove the second dielectric layer 102c, charge storage layer 102b, and first dielectric layer 102a on logic device area 100b. Thereafter, a threshold voltage (Vt) region (not shown in FIG.) is formed on substrate 100 by ion implanting process 106. Because the second dielectric layer 102c is touched the photoresist layer 104 many times, the thickness of second dielectric layer 102c is to be thinned and the characteristic of second dielectric layer 102c is to be changed.
Then, referring to FIG. 1C, a gate oxide layer 108 is formed on the logic device area 100b, after the photoresist layer 104 is removed, and a polysilicon layer 110 is deposited on the memory array area 100a and logic device area 100b. 
Referring to FIG. 1D, a plurality of word line is defined on the memory array area 100a and another photoresist layer (not shown) is formed on the polysilicon layer 110. Then, an etching process is performed on the polysilicon layer 110 to form the polysilicon gate electrode 110 on the memory array area 100a and on the logic device area 100b simultaneously.
Referring to FIG. 1E, a silicon oxide layer is deposited to fill the pitch between the polysilicon gate electrodes 110. Then, an etching-back process is performed on the silicon oxide layer to form spacers 112 on sidewalls of the polysilicon gate electrodes 110. Then, a self-aligned silicide process is formed over the polysilicon gate electrode 110.
Referring to FIG. 1F is a vertical view of the memory device. The horizontal lines connected to all the cells in the row are called the word lines 114a, 114b, 114c, and 114d, and the vertical lines along which the data flows into and out of the cells are called bit lines 116a, 116b, 116c, and 116d. The dotted line 120 is crosscut the word lines 114a, 114b, 114c, and 114d. Due to the thickness of the ONO layer 102 is too thin, thus, the silicide layer will pass through the ONO layer 102 to the substrate 100 in self-aligned silicide process such that the semiconductor device will not be operated.
According to above-mentioned description, the silicon oxide layer for forming separated spacers width between the polysilicon gate electrodes is not enough to create a safe oxide thickness so that the conduction film will be formed from self-aligned silicide process between the bit lines to bit lines and the leakage path is also occurred between the bit lines to the bit lines. And the most obvious limiting factor for an embedded flash memory is the relevant fabrication. In conventional fabrication, the transistors of the memory array area and the logic device area are formed simultaneously; therefore, the quality of the transistor of both memory array area and logic device area cannot be optimized at the same time. In other words, either performance of any transistors of the logic device area is degraded or reliability of any memory array area is degraded.
It is an object of this invention to provide a first polysilicon layer as a protective layer that is formed on the transistors of the memory array area to protect the ONO layer (oxide/nitride/oxide layer) from touches the photoresist layer in threshold voltage ion implantation on the logic device area.
It is another object of this invention to use a self-aligned silicide layer on the first polysilicon gate electrode on the memory array area as an etching-stop layer for etching the second polysilicon layer to form the second polysilicon gate electrode on the logic device area.
It is still another object of this invention to use a separated spacers width on the memory array area and on the logic device area to avoid the leakage path between the bit lines to the bit lines in a self-aligned silicide process.
In one embodiment, the present invention provides a method for forming an embedded non-volatile memory cell comprises the steps of providing a substrate and an ONO layer thereon. In the present invention, the ONO layer is formed earlier than the formation of the plurality of bit lines structure. Then, the first polysilicon layer is formed on the ONO layer. In order to get optimum process window, the transistor on the memory array area and on the logic device area are formed by two separated adjust photolithography conditions, and to avoid the leakage path between the bit lines to bit lines in a self-aligned silicide process. Furthermore, the separated spacers width between the polysilicon gate electrode on the memory array area and on the logic device area is filled by the oxide layer. Then, a second polysilicon layer is formed on the transistor of the memory array area and used as an insulation film to avoid the ONO layer on the memory array area that is touched by photoresist layer in threshold voltage ion implantation on the logic device area.